1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a method for setting replacement information in a nonvolatile semiconductor memory. More specifically, the present invention relates to a nonvolatile semiconductor memory and a method for setting replacement information in the nonvolatile semiconductor memory, in which a method for storing replacement data is improved.
2. Description of the Related Art
There has been known a nonvolatile semiconductor memory that includes a plurality of main cell arrays, a plurality of redundant cell arrays, and a replacement data storage unit. Each of the redundant memory cell arrays replaces a defect one of the main cell arrays. The replacement data storage unit stores the replacement data indicating which of the main cell arrays is replaced by which of the redundant cell arrays.
Whenever the nonvolatile semiconductor memory is accessed in a write operation, a read operation or the like, the replacement data stored in the replacement data storage unit is referred to. Each of the operations is executed based on the referring result. It is, therefore, necessary to promptly and accurately access the replacement data. A technique that enables promptly and accurately accessing the replacement data is desired.
Meanwhile, the replacement data stored in the replacement data storage unit is stored when the nonvolatile semiconductor memory is manufactured. Since it is preferable that time required to manufacture it is as short as possible, it is desired to store the replacement data within time as short as possible. Besides, it is required to accurately store the replacement data.
In conjunction with the above description, Japanese Patent JP 2537264B discloses a semiconductor memory apparatus. This semiconductor memory apparatus includes a memory cell array, a write circuit, a differential amplification type sense amplifier, a latch circuit, and setting means. The memory cell array includes many memory cells with two writable nonvolatile memory cells selected by the same word line selection signal and the same column selection signal as one bit. The write circuit writes complementary bit data to the two memory cells through a pair of bit lines to which the corresponding pair memory cells are connected, respectively. The differential amplification type sense amplifier amplifiers a potential difference between the paired bit lines and judges read data. The latch circuit temporarily latches a content of write data input in a write operation. The setting means sets a data judgment criterion during verification right after data is written to be stricter than a judgment criterion during a normal read operation based on latch data stored in the latch circuit.
Japanese Laid Open Patent Application JP 2002-237191A discloses a complementary nonvolatile memory circuit. This nonvolatile memory circuit is a nonvolatile memory circuit using FLOTOX (floating gate tunnel oxide) type electrically writable nonvolatile storage elements. The nonvolatile memory circuit includes a first data line and a second data line. A drain of a first nonvolatile storage element is connected to the first data line through at least one first selected transistor. A drain of a second nonvolatile storage element is connected to the second data line through at least one second selected transistor. A gate of the first nonvolatile storage element is connected to a drain of a second nonvolatile storage element. A gate of the second nonvolatile storage element is connected to a drain of the first nonvolatile storage element. The first data line is connected to a first current load circuit and a first input terminal of a sense amplifier circuit. The second data line is connected to a second current load circuit and a second input terminal of the sense amplifier circuit. Sources of the first nonvolatile storage element and the second nonvolatile storage elements are connected to a ground potential through switching transistors, respectively. This nonvolatile memory circuit is characterized by always storing complementary pairs of positive and negative logic states of one-bit data using the first and second nonvolatile storage elements.